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PC Hardware in a Nutshell, 3rd Edition by Barbara Fritchman Thompson, Robert Bruce Thompson

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SCSI Implementations

SCSI implementations are characterized by their width (bits transferred per clock cycle), clock rate, and overall throughput, which is the product of those two figures. Bus width determines how much data is transferred per clock cycle, and may be either of the following:

Narrow SCSI

Narrow SCSI transfers one byte per clock cycle, using a one-byte wide data bus on a 50-pin parallel interface, which is defined by SCSI-1.

Wide SCSI

Wide SCSI transfers two bytes per clock cycle, using a two-byte wide data bus on a 68-pin parallel interface, which is defined by the SCSI-3 SPI document. Although SCSI-3 allows bus widths greater than two bytes, all current Wide SCSI implementations use two bytes.

The signaling rate (or clock rate), properly denominated in MegaTransfers/Second (MT/s) but more commonly stated in MHz, specifies how frequently transfers occur. Various SCSI implementations use signaling rates of 5 MHz, 10 MHz, 20 MHz, 40 MHz, and 80 MHz, which are given the following names:

SCSI

SCSI when used without qualification to describe a transfer rate refers to the 5 MT/s transfer rate defined in SCSI-1. Because SCSI-1 supports only narrow (8-bit) transfers, SCSI-1 transfers 5 MB/s (5 MT/s × 1 byte/transfer).

Fast SCSI

Fast SCSI describes the 10 MT/s transfer rate defined in SCSI-2. Used with a narrow interface (called Fast Narrow SCSI or simply Fast SCSI), transfers 10 MB/s (10 MT/s × 1 byte/transfer). Used with a wide interface, called Fast Wide SCSI, transfers ...

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