PCI Express System Architecture

Flow Control Buffers

Flow control buffers are implemented for each VC resource supported by a PCI Express port. Recall that devices at each end of the link may not support the same number of VC resources, therefore the maximum number of VCs configured and enabled by software is the greatest number of VCs in common between the two ports.

VC Flow Control Buffer Organization

Each VC Flow Control buffer at the receiver is managed for each category of transaction flowing through the virtual channel. These categories are:

• Posted Transactions — Memory Writes and Messages

• Non-Posted Transactions — Memory Reads, Configuration Reads and Writes, and I/O Reads and Writes

• Completions — Read Completions and Write Completions

In addition, each of these categories ...