Message Signaled Interrupts (MSIs) are delivered to the Root Complex via memory write transactions. The MSI Capability register provides all the information that the device requires to signal MSIs. This register is set up by configuration software and includes the following information:
Target memory address
Data Value to be written to the specified address location
The number of messages that can be encoded into the data
See “Description of 3DW And 4DW Memory Request Header Fields” on page 176 for a review of the Memory Write Transaction Header. Note that MSIs always have a data payload of 1DW.
A PCI Express function indicates its support for MSI via the MSI Capability registers. Each ...