PCI Express System Architecture

Reset Exit

After exiting the reset state, Link training and initialization must begin within 80 ms. Devices may exit the reset state at different times, since reset signaling is asynchronous. This means that in fact two devices on opposite ends of the Link who are reset may not start the Link training process at the same time.

After Link Training and Initialization each device proceeds through Flow Control initialization for VC0, making it possible for TLPs and DLLPs to be transferred across the Link.

To allow components who have been reset to perform internal initialization, system software must wait for at least 100 ms from the end of a reset (cold/warm/hot) before issuing Configuration Requests to PCI Express devices. To be software visible, ...