Refer to Figure 21-8 on page 757. In a system with multiple Root Complexes, each Root Complex:
Implements the Configuration Address Port and the Configuration Data Port at the same IO addresses (if it's an x86-based system).
Implements the Enhanced Configuration Mechanism.
Contains a Host/PCI bridge.
Implements the Bus Number and Subordinate Bus Number registers at separate addresses known to the configuration software.
In the example illustration, each Root Complex is a member of the chipset and one of them is designated as the bridge to bus 0 (let's call this the ...