PCI Express System Architecture

Introduction

Refer to Figure 24-1 on page 895. As described earlier in “Each Function Implements a Set of Configuration Registers” on page 715, each PCI Express function has a dedicated 4KB memory address range within which its configuration registers are implemented. Each Express function must implement the PCI Express Capability register set somewhere in the lower 48 dwords of the PCI-compatible register space (i.e., within the lower 48 dword region of the first 64 dwords of configuration space). In addition, the function may optionally implement any of the PCI Express Extended Capability register sets. The sections that follow provide a detailed description of each of these Express-specific register sets.

Figure 24-1. Function's Configuration ...