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Performance and Fault Management by James M. Thompson, Kent J. Phelps, Robert L. Pavone, Christopher E. Elliott, Paul L. Della Maggiora

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Fault Management for ATM Interfaces

Fault management for ATM interfaces involves monitoring for errors at the various levels of the ATM stack. There may be bit errors at the ATM level or SAR errors at the AAL5 level. The errors may be due to bad media, interface hardware, or internal resource limitations. This section covers the meaning of different error counters from both the MIB and the CLI.

Some standard errors are as follows:

  • HEC errors: The HEC (Header Error Control) in the ATM cell header is an 8-bit CRC code. HEC errors would be similar to FCS errors in Ethernet (see the “Error/Fault Monitoring” section in Chapter 12.

  • SAR timeouts: For the AAL5 layer—this error indicates CPCS PDUs that are discarded because they were not reassembled in ...

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