Physical Design for 3D Integrated Circuits

4	3D Interconnect Extraction Sung Kyu Lim

CONTENTS

Abstract

4.1    Introduction

4.2    TSV-to-TSV Coupling Extraction

4.2.1    Two-TSV vs. Multi-TSV Model

4.2.2    Silicon and E-Field Distribution Impacts

4.2.3    TSV-to-TSV Coupling Impact on Full-Chip Noise

4.2.4    Full-Chip TSV-to-TSV Coupling Mitigation

4.3    TSV-to-Wire Coupling Extraction

4.3.1    E-Field Sharing Impact

4.3.2    Pattern-Matching Technique

4.3.3    TSV-to-Wire Coupling Impact on Full-Chip Noise

4.3.4    Full-Chip TSV-to-Wire Coupling Mitigation

4.4    Conclusions

References

ABSTRACT

Through-silicon-via (TSV) introduces new parasitic components into 3D ICs. They penetrate silicon substrate and are vulnerable to any signal noise through the substrate. They also introduce ...