Physical Design for 3D Integrated Circuits

9	Live Free or Die Hard Design for Reliability in 3D Integrated Circuits Yu-Guang Chen, Yiyu Shi, and Shih-Chieh Chang

CONTENTS

Abstract

9.1    Reliability Issues in 3D-IC Designs

9.2    Spare TSVs and Fault-Tolerant Structures

9.2.1    Double TSV Technique

9.2.2    Shared-Spare TSV Technique

9.3    Design Constraints

9.3.1    Chip Yield Constraint

9.3.2    Timing Constraint

9.3.3    TSV Placement

9.4    Fault-Tolerance for Signal TSV

9.4.1    Assumptions and Problem Formulation

9.4.2    Algorithm

9.4.2.1    Graph Perspective

9.4.2.2    Undirected Graph-Based Heuristic

9.4.2.3    Directed Graph-Based Heuristic

9.4.3    Experimental Results

9.5    Fault-Tolerance for Clock Network

9.5.1    Challenge of Reliability about 3D Clock Networks ...