Chapter 14
Optimizing Cache Usage
Abstract
This chapter covers the fundamentals of processor caches and how temporal and spatial data locality affect performance. Section 14.1 covers the organization of the cache. Section 14.2 demonstrates how to dynamically determine the topology. Section 14.3 covers both hardware and software prefetching. Section 14.4 covers techniques for improving cache utilization.
Keywords
Cache
Ways
Associative cache
PAT
MTRR
Cache line
Cacheline
Streaming instructions
Prefetch
LLC
L1
L2
L3
AOS
SOA
Array of structs
Struct of arrays
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