Chapter 8. Power Integrity-Aware Chip Floorplanning and Design
Shane Stelmach and Snehamay Sinha
The modern chip designer is required to make many complex and mutually dependent trade-offs. Power integrity (PI) is among these. Generally, one must find the most economical way to meet certain functionality and performance requirements: The design’s PI must be adequate to meet these goals. The responsibility for this is shared between various designers, including the chip architect, the logic designer, the physical layout designer, and the package designer, as well as the system team for the greater product. The integrated circuit (IC) design team focuses on areas impacting PI such as average and peak power management as well as chip floorplanning ...
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