Power Integrity for I/O Interfaces: With Signal Integrity/Power Integrity Co-Design

Chapter 1. Introduction

In a digital electronic system, when high-speed signals pass through the interconnect network, different unwanted effects such as Inter Symbol Interference (ISI) and crosstalk are produced that degrade the signal integrity. Power integrity is related to noise in the Power Distribution Network (PDN). Various techniques have been developed to model and design the PDN and analyze the noise impact [1, 2]. Simultaneously Switching Output (SSO) noise is produced when charging/discharging currents from the multiple buffers go through the PDN. This noise affects the circuit response and produces timing skews and delays. The power noise is coupled to signals at the chip level and at the interconnect level. It is becoming increasingly ...