55DC-DC Converter Design and Magnetics
the MAX of the current limit speciﬁ
cation. So, in this case, a “ loose ” current limit
speciﬁ cation effectively amounts to requiring bigger components (transformer) for the
same maximum power-handling capability.
Note: Some makers of off-line integrated switcher ICs (e.g., the “ Topswitch ” from
Power Integrations) often tout their “ precise ” current limit, thus suggesting that
we get the best power-to-size ratio (i.e., converter power density) when using their
products. However, we should remember that in most cases, their product families
have a discrete set of ﬁ xed current limits. And that is a problem! For example, we
may have devices available with current limits in steps of 2 A, 3 A, 4 A, and so on.
So yes, we may indeed get a higher power density when operating at the maximum rated
output power of a particular IC. But when operating at a power level between available
current limits, we are not going to get an optimum solution. For example, in an
application where the peak current is 2.2 A, then we would need to select the 3 A
current limit part, and we will need to design our magnetics to avoid core saturation
at 3 A. So in effect, we have a very imprecise current limit now! The best solution is
to look for a part (integrated switcher or controller plus MOSFET solution) where
we can precisely set the current limit externally , depending upon our application.
With all these subtle considerations in mind, a designer can hopefully pick a more
appropriate inductor current rating for his or her application. Clearly, there are no hard
and fast rules. Engineering judgment needs to be applied as usual, and perhaps some
further bench-testing may also be needed to validate the ﬁ nal choice of inductor.
In the worked examples that follow, the general approach and design procedure will
3.15 Worked Example (1)
A boost converter has an input range of 12 V to 15 V, a regulated output of 24 V, and a
maximum load current of 2 A. What would be a reasonable goal for its inductance, if the
switching frequency is (a) 100 kHz, (b) 200 kHz, and (c) 1 MHz? What is the peak current
in each case? And what is the energy-handling requirement?
The ﬁ rst thing we have to remember is that, for this topology (as for the buck-boost), the
worst-case is the lowest end of the input range, since that corresponds to the highest duty
cycle and thus the highest average current I
/(1 D ). So for all practical purposes,
we can completely disregard V
here—in fact it was a red herring to start with, for
this particular analysis!