book

Practical FPGA Programming in C

Name: Practical FPGA Programming in C
ISBN: 0131543180

by David Pellerin, Scott Thibault

April 2005

Intermediate to advanced

464 pages

9h 48m

English

Pearson

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Copyright
Dedication
Prentice Hall Modern Semiconductor Design Series
Foreword
Why is this book of interest to the hardware folks?And what about the software guys and gals?So what's the catch?
Preface
C Language for FPGA-Based Hardware Design?Compelling Platforms for Software AccelerationThe Power to ExperimentHow This Book Is OrganizedWhere This Book Came From
Acknowledgments
1. The FPGA as a Computing Platform
1.1. A Quick Introduction to FPGAsCommon FPGA CharacteristicsFPGA Programming Technologies1.2. FPGA-Based Programmable Hardware Platforms1.3. Increasing Performance While Lowering Costs1.4. The Role of ToolsAn Emphasis on Software-Based Methods1.5. The FPGA as an Embedded Software Platform1.6. The Importance of a Programming Abstraction1.7. When Is C Language Appropriate for FPGA Design?1.8. How to Use This Book
2. A Brief History of Programmable Platforms
2.1. The Origins of Programmable LogicNew Methods of Design Are RequiredEarly HDLs Increase Design AbstractionLarger Devices, More-Complex Programming Tools2.2. Reprogrammability, HDLs, and the Rise of the FPGA2.3. Systems on a Programmable ChipToward Faster System Prototypes and Higher Performance2.4. FPGAs for Parallel ComputingReconfigurable Computing and the FPGA2.5. Summary
3. A Programming Model for FPGA-Based Applications
3.1. Parallel Processing ModelsSISD: The Original Processor Machine ModelThe SIMD Machine ModelMIMD Machines and the TransputerShared Memory MIMD Architectures3.2. FPGAs as Parallel Computing MachinesAdding Soft Processors to the Mix3.3. Programming for Parallelism3.4. Communicating Process Programming Models3.5. The Impulse C Programming Model3.6. Summary
4. An Introduction to Impulse C
4.1. The Motivation Behind Impulse C4.2. The Impulse C Programming Model4.3. A Minimal Impulse C ProgramThe Software Source File: HelloFPGA_sw.cThe Hardware Source File: HelloFPGA_hw.c4.4. Processes Streams Signals, and Memory4.5. Impulse C Signed and Unsigned Datatypes4.6. Understanding ProcessesCreating Processes4.7. Understanding StreamsStream I/O4.8. Using Output Streams4.9. Using Input StreamsChecking for End of StreamEfficient Use of Stream ReadsMethod 1 (preferred method)Method 2 (acceptable method)Method 3 (less acceptable)4.10. Avoiding Stream DeadlocksUsing Nonblocking Stream ReadsDeadlocks and the PIPELINE Pragma4.11. Creading and Using Signals4.12. Understanting RegistersControlling Registers from Software Processes4.13. Using Shared Memories4.14. Memory and Stream Performance ConsiderationsMicro-Benchmark IntroductionMemory Test Results for the Altera Nios PlatformMemory Test Results for the Xilinx PowerPC PlatformMemory Test Results for the Xilinx MicroBlaze Platform4.15. Summary
5. Describing a FIR Filter
5.1. Design Overview5.2. The FIR Filter Hardware Process5.3. The Software Test BenchThe Producer ProcessThe Consumer Process5.4. Desktop Simulation5.5. Application MonitoringMonitoring with Log Windows5.6. Summary

6. Generating FPGA Hardware
6.1. The Hardware Generation FlowOptimization and Hardware Generation6.2. Understanding the Generated Structure6.3. Stream and Signal InterfacesStream and Signal ProtocolsStreams Used in Write ModeStreams Used in Read ModeSignals Used in Post (Write) ModeSignals Used in Wait (Read) Mode6.4. Using HDL Simulation to Understand Stream Protocols6.5. Debugging the Generated Hardware6.6. Hardware Generation NotesInstruction-Level PragmasPragma CO PIPELINEPragma CO UNROLLPragma CO SET StageDelayUnderstanding Latency and RateControlling Stage Delays6.7. Making Efficient Use of the OptimizersThe Stage Master OptimizerInstruction Scheduling and AssignmentsImpacts of Memory Access6.8. Language Constraints for Hardware ProcessesNo Support for Hardware Function CallsInteger Math OperationsShift OperationsSupport for Datatypes Is LimitedLimited Support for PointersUsing Pointers with Multidimensional Arrays6.9. Summary
7. Increasing Statement-Level Parallelism
7.1. A Model of FPGA Computation7.2. C Language Semantics and Parallelism7.3. Exploiting Instruction-Level ParallelismInstruction SchedulingPipeline GenerationOptimizer OperationExpression-Level OptimizationsOptimization Within Basic Blocks7.4. Limiting Instruction StagesReduce Memory Accesses for Higher PerformanceArray Splitting7.5. Unrolling Loops7.6. Pipelining ExplainedPipeline Rate7.7. Summary
8. Porting a Legacy Application to Impulse C
8.1. The Triple-DES Algorithm8.2. Converting the Algorithm to a Streaming Model8.3. Performing Software Simulation8.4. Compiling To Hardware8.5. Preliminary Hardware AnalysisInitial Results: 10.6X Performance Increase8.6. Summary
9. Creating an Embedded Test Bench
9.1. A Mixed Hardware and Software ApproachConsidering Data Transfer Overhead9.2. The Embedded Processor as a Test GeneratorA Unit Test PhilosophyDesktop Simulation Versus Embedded Test BenchesData Throughput and Processor SelectionMoving Test Generators to Hardware9.3. The Role of Hardware Simulators9.4. Testing the Triple-DES Algorithm in HardwarePlatform SelectionSoftware and Hardware Algorithm Comparison9.5. Software Stream Macro Interfaces9.6. Building the Test SystemSpecifying the Platform Support PackageGenerating HDL for the Hardware ProcessCreating the Platform Using the Xilinx ToolsCreating a Platform Studio Project and Choosing a BoardConfiguring the MicroBlaze ProcessorExporting Files from the Impulse ToolsImporting the Generated HardwareAdding the 3DES Hardware IP CoreSetting the FSL Bus Parameters and Connections for the CoreAdding and Configuring an OPB Timer CoreSpecifying the Peripheral AddressesSpecifying the System Clock PinImporting the Application SoftwareGenerating the FPGA BitmapDownloading and Running the Application9.7. Summary
10. Optimizing C for FPGA Performance
10.1. Rethinking an Algorithm for Performance10.2. Refinement 1: Reducing Size by Introducing a Loop10.3. Refinement 2: Array Splitting10.4. Refinement 3: Improving Streaming Performance10.5. Refinement 4: Loop Unrolling10.6. Refinement 5: Pipelining the Main LoopUsing Stage Master ExplorerThe Goal of Pipelining10.7. Summary
11. Describing System-Level Parallelism
11.1. Design Overview11.2. Performing Desktop Simulation11.3. Refinement 1: Creating Parallel 8-Bit Filters11.4. Refinement 2: Creating a System-Level PipelineThe DMA Input ProcessThe Column Generator ProcessThe Image Filter ProcessThe Stream to Memory ProcessThe Configuration Function11.5. Moving the Application to HardwareGenerating the FPGA HardwareExporting the Generated FilesCreating a New Quartus and SOPC Builder ProjectCreating the New Platform Using SOPC BuilderConfiguring the FPGA PlatformAdding Nios II PeripheralsThe Timer PeripheralExternal Flash Memory InterfaceExternal RAM InterfaceJTAG UART InterfaceExternal RAM Bus (Avalon Tri-State Bridge)Adding the Hardware Process Module (img_arch)Setting Additional CPU SettingsGenerating the SystemConnecting the Generated System to FPGA PinsFPGA Pin AssignmentGenerating the FPGA BitmapRunning the Test Application on the Platform11.6. Summary
12. Combining Impulse C with an Embedded Operating System
12.1. The uClinux Operating SystemCombining uClinux and Impulse C12.2. A uClinux Demonstration ProjectThe Impulse C Project FilesBuilding the Application for the Target PlatformCopying the Sample uClinux Platform FilesSpecifying the Platform Support PackageBuilding the Image Filter HardwareExporting the Software and HardwareModifying the Sample uClinux PlatformConfiguring the Platform with the Image Filter IP CoreMaking the FSL ConnectionsConnecting the Image Filter Clock and Reset LinesGenerating the FPGA BitmapDownloading the Kernel ImageBuilding and Testing the Image Filter SoftwareUsing TFTP to Transfer Files to the BoardRunning the Image Filter Program12.3. Summary
13. Mandelbrot Image Generation
13.1. Design OverviewThe Mandelbrot SetAccuracy Versus Processing Requirements13.2. Expressing the Algorithm in C13.3. Creating a Fixed-Point Equivalent13.4. Creating a Streaming VersionThe Impulse C Process13.5. Parallelizing the AlgorithmPartitioning the ProblemOutput SynchronizationThe Configuration Function13.6. Future Refinements13.7. Summary
14. The Future of FPGA Computing
14.1. The FPGA as a High-Performance ComputerTaking Parallelism to Extreme LevelsMany Platforms to Choose FromTaking a Software Approach14.2. The Future of FPGA ComputingBigger FPGAs and Increased System Integration14.3. Summary
A. Getting the Most Out of Embedded FPGA Processors
A.1. FPGA Embedded Processor OverviewSoft Versus Hard ProcessorAdvantages of an FPGA Embedded ProcessorCustomizationObsolescence MitigationComponent and Cost ReductionHardware AccelerationDisadvantagesA.2. Peripherals and Memory ControllersPeripheral TypesMemory ControllersA.3. Increasing Processor PerformanceManufacturers' BenchmarksPerformance-Enhancing TechniquesA.4. Optimization Techniques That Are Not FPGA-SpecificCode ManipulationOptimization LevelUse of Manufacturer-Optimized InstructionsAssemblyMiscellaneousMemory UsageLocal Memory OnlyExternal Memory OnlyCache External MemoryPartitioning Code into Internal, External, and Cached MemoryA.5. FPGA-Specific Optimization TechniquesIncreasing the FPGA's Operating FrequencyLogic Optimization and ReductionArea and Timing ConstraintsHardware AccelerationTurn on the Hardware Divider and Barrel-ShifterSoftware Bottlenecks Converted to Coprocessing HardwareA.6. SummaryHave Reasonable ExpectationsOptimization Through Experimentation Yields the Best ResultsTake Advantage of Superior Flexibility in FPGAsAcknowledgments
B. Creating a Custom Stream Interface
B.1. Application OverviewB.2. The DS92LV16 Serial Link for Data StreamingInitializing the Serial ConnectionB.3. Stream Interface State Machine DescriptionState: send_syncState: send_sync_240 State: send_flags_240State: send_ack1State: send_ack2State: connectedB.4. Data TransmissionFuture RefinementsB.5. Summary
C. Impulse C Function Reference
CO_ARCHITECTURE_CREATEHeader FileDescriptionArgumentsReturn ValueNotesCO_BIT_EXTRACTHeader FileDescriptionArgumentsReturn ValueNotesCO_BIT_EXTRACT_UHeader FileDescriptionArgumentsReturn ValueNotesCO_BIT_INSERTHeader FileDescriptionArgumentsReturn ValueNotesCO_BIT_INSERT_UHeader FileDescriptionArgumentsReturn ValueNotesCO_EXECUTEHeader FileDescriptionArgumentsReturn ValueNotesCO_INITIALIZEHeader FileDescriptionArgumentsReturn ValueNotesCO_MEMORY_CREATEHeader FileDescriptionArgumentsReturn ValueNotesCO_MEMORY_PTRHeader FileDescriptionArgumentsReturn ValueNotesCO_MEMORY_READBLOCKHeader FileDescriptionArgumentsReturn ValueNotesCO_MEMORY_WRITEBLOCKHeader FileDescriptionArgumentsReturn ValueNotesCO_PAR_BREAKHeader FileDescriptionArgumentsReturn ValueNotesCO_PROCESS_CONFIGHeader FileDescriptionArgumentsReturn ValueNotesCO_PROCESS_CREATEHeader FileDescriptionArgumentsReturn ValueNotesCO_REGISTER_CREATEHeader FileDescriptionArgumentsReturn ValueNotesCO_REGISTER_GETHeader FileDescriptionArgumentsReturn ValueCO_REGISTER_PUTHeader FileDescriptionArgumentsReturn ValueNotesCO_REGISTER_READHeader FileDescriptionArgumentsReturn ValueCO_REGISTER_WRITEHeader FileDescriptionArgumentsReturn ValueCO_SIGNAL_CREATEHeader FileDescriptionArgumentsReturn ValueNotesCO_SIGNAL_POSTHeader FileDescriptionArgumentsReturn ValueNotesCO_SIGNAL_WAITHeader FileDescriptionArgumentsReturn ValueNotesCO_STREAM_CLOSEHeader FileDescriptionArgumentsReturn ValueNotesCO_STREAM_CREATEHeader FileDescriptionArgumentsReturn ValueNotesCO_STREAM_EOSHeader FileDescriptionArgumentsReturn ValueNotesCO_STREAM_OPENHeader FileDescriptionArgumentsReturn ValueCO_STREAM_READHeader FileDescriptionArgumentsReturn ValueNotesCO_STREAM_READ_NBHeader FileDescriptionArgumentsReturn ValueNotesCO_STREAM_WRITEHeader FileDescriptionArgumentsReturn ValueNotesCOSIM_LOGWINDOW_CREATEHeader FileDescriptionArgumentsReturn ValueCOSIM_LOGWINDOW_FWRITEHeader FileDescriptionArgumentsReturn ValueCOSIM_LOGWINDOW_INITHeader FileDescriptionArgumentsReturn ValueCOSIM_LOGWINDOW_WRITEHeader FileDescriptionArgumentsReturn Value
D. Triple-DES Source Listings
DES_HW.CDES.CDES_SW.CDES.H
E. Image Filter Listings
IMG_HW.CIMG_SW.CIMG.H
F. Selected References

Content preview from Practical FPGA Programming in C

Chapter 5. Describing a FIR Filter

In this chapter we present a simple digital filtering application in order to more fully introduce concepts of streams-based programming and to demonstrate the use of desktop simulation for design verification. In subsequent chapters we'll describe the process of actual hardware generation and discuss how to take advantage of statement-level and system-level parallelism for increased process throughput.

Design Overview

A finite impulse response (FIR) filter is a type of signal processing element whose output is determined by a weighted sum of its past and present input values. There are many types of digital FIR filters, but all are defined primarily by the size of the window (number of discrete historical samples) ...

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Practical FPGA Programming in C

by David Pellerin, Scott Thibault

Chapter 5. Describing a FIR Filter

Design Overview

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