Chapter 10. Optimizing C for FPGA Performance

In Chapters 8 and 9 we presented a triple-DES encryption algorithm, showing how a process of software simulation, using standard C tools coupled with in-system testing, could be used to validate a legacy C algorithm that had been converted to an FPGA implementation. As we pointed out in those chapters, however, the performance obtained from this particular algorithm was not especially good relative to what could be achieved by a reasonably skilled VHDL or Verilog programmer.

C code that has not been written with hardware compilation in mind can result in less-than-optimal results when those results are measured in terms of process latencies, data throughput, and size of the generated logic. This is ...

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