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Programming Embedded Systems, 2nd Edition
book

Programming Embedded Systems, 2nd Edition

by Michael Barr, Anthony Massa
October 2006
Intermediate to advanced content levelIntermediate to advanced
336 pages
9h 13m
English
O'Reilly Media, Inc.
Content preview from Programming Embedded Systems, 2nd Edition

A Quick Look at Makefiles

You can imagine how tedious the build process could be if you had a large number of source code files for a particular project. Manually entering individual compiler and linker commands on the command line becomes tiresome very quickly. In order to avoid this, a makefile can be used. A makefile is a script that tells the make utility how to build a particular program. (The make utility is typically installed with the other GNU tools.) The make utility follows the rules in the makefile in order to automatically generate output files from a set of input source files.

Makefiles might be a bit of a pain to set up, but they can be a great timesaver and a very powerful tool when building project files over and over (and over) again. Having a sample available can reduce the pain of setting up a makefile.

The basic layout for a makefile build rule is:

target:   prerequisite
          command

The target is what is going to be built, the prerequisite is a file that must exist before the target can be created, and the command is a shell command used to create the target. There can be multiple prerequisites on the target line (separated by white space) and/or multiple command lines. But be sure to put a tab, not spaces, at the beginning of every line containing a command.

Here’s a makefile for building our Blinking LED program:

XCC = arm-elf-gcc LD = arm-elf-ld CFLAGS = -g -c -Wall \\ -I../include LDFLAGS = -Map blink.map -T viperlite.ld -N all: blink.exe led.o: led.c led.h $(XCC) ...
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Publisher Resources

ISBN: 0596009836Supplemental ContentErrata Page