Skip to Main Content
Programming Massively Parallel Processors, 3rd Edition
book

Programming Massively Parallel Processors, 3rd Edition

by David B. Kirk, Wen-mei W. Hwu
November 2016
Intermediate to advanced content levelIntermediate to advanced
576 pages
18h 22m
English
Morgan Kaufmann
Content preview from Programming Massively Parallel Processors, 3rd Edition
Chapter 5

Performance considerations

Abstract

In this chapter, we reviewed the major aspects of application performance on a CUDA device: global memory access coalescing, memory parallelism, control flow divergence, dynamic resource partitioning and instruction mixes. Each of these aspects is rooted in the hardware limitations of the devices. Based on these concepts, we introduce techniques for analyzing the code for memory coalescing, channel/bank utilization, and control divergence. More importantly, we introduce techniques for converting poor performing code into well performing code: corner-turning, active thread index consolidation, and thread granularity coarsening.

Keywords

Compute-bound; memory-bound; bottleneck; memory bandwidth; DRAM burst; ...

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Programming Massively Parallel Processors, 4th Edition

Programming Massively Parallel Processors, 4th Edition

Wen-mei W. Hwu, David B. Kirk, Izzat El Hajj
Engineering a Compiler, 2nd Edition

Engineering a Compiler, 2nd Edition

Keith D. Cooper, Linda Torczon
Algorithms, 4th Edition

Algorithms, 4th Edition

Robert Sedgewick, Kevin Wayne

Publisher Resources

ISBN: 9780128119877