May 2022
Intermediate to advanced
580 pages
18h 32m
English
book
Programming Massively Parallel Processors, 4th Edition
by Wen-mei W. Hwu, David B. Kirk, Izzat El Hajj
Content preview from Programming Massively Parallel Processors, 4th Edition
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Chapter 6
Performance considerations
Abstract
In this chapter we briefly present the off-chip memory (DRAM) architecture and discuss related performance considerations, such as memory coalescing and memory latency hiding. We then discuss an important optimization, thread granularity coarsening, that may target any of the different aspects of the compute and memory architecture, depending on the application. Finally, we wrap up this part of the book with a checklist of common performance optimizations that will serve as a guide for optimizing the performance of the parallel patterns that are discussed in the second and third parts of the book.
Keywords
Memory bandwidth; memory bank; memory channel; DRAM burst; memory coalescing; corner turning; latency ...
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