Book description
Quick Boot is designed to give developers a background in the basic architecture and details of a typical boot sequence. More specifically, this book describes the basic initialization sequence that allows developers the freedom to boot an OS without a fully featured system BIOS. Various specifications provide the basics of both the code bases and the standards. This book also provides insights into optimization techniques for more advanced developers. With proper background information, the required specifications on hand, and diligence, many developers can create quality boot solutions using this text.
Pete Dice is Engineering Director of Verifone, where he manages OS Engineering teams in Dublin, Ireland and Riga Latvia. Dice successfully launched Intel® Quark™, Intel's first generation SoC as well as invented the Intel® Galileo™ development board and developed a freemium SW strategy to scale Intel IoT gateway features across product lines. He is also credited with architecting the "Moon Island" software stack and business model.
Table of contents
- Cover
- Title Page
- Copyright
- Contents
- Chapter 1: System Firmware’s Missing Link
- Chapter 2: Intel Architecture Basics
- Chapter 3: System Firmware Terms and Concepts
- Chapter 4: Silicon-Specific Initialization
- Chapter 5: Industry Standard Initialization
- Chapter 6: System Firmware Debug Techniques
- Chapter 7: Shells and Native Applications
- Chapter 8: Loading an Operating System
-
Chapter 9: The Intel ® Architecture Boot Flow
- Hardware Power Sequences (The Pre-Pre-Boot)
- Early Initialization
-
Advanced Initialization
- General Purpose I/O (GPIO) Configuration
- Interrupt Controllers
- Interrupt Vector Table (IVT)
- Interrupt Descriptor Table (IDT)
- Timers
- Memory Caching Control
- Serial Ports
- Clock and Overclock Programming
- PCI Device Enumeration
- Graphics Initialization
- Input Devices
- USB Initialization
- SATA Initialization
- SATA Controller Initialization
- Memory Map
- Loading the OS
- Summary
-
Chapter 10: Bootstrapping Embedded
- Optimization Using BIOS and Bootloaders
- Case Study Summaries
-
Example 1 Details
- What Are the Design Goals?
- What Are the Supported Target Operating Systems?
- Do We Have to Support Legacy Operating Systems?
- Do We Have to Support Legacy Option ROMs?
- Are We Required to Display an OEM Splash Screen?
- What Type of Boot Media Is Supported?
- What Is the BIOS Recovery/Update Strategy?
- When Processing Things Early
- Is There a Need for Pre-OS User Interaction?
- A Note of Caution
- Additional Details
-
Example 2 Details
- Turn Off Debugging
- Decrease Flash Size
- Caching of PEI Phase
- Intel SpeedStep® Technology Enabled Early
- BDS Phase Optimization
- Platform Memory Speed
- Remove PS/2 Keyboard/Mouse
- Remove BIOS Setup
- Remove Video Option ROM
- Remove BIOS USB Support
- Divide Long Lead Pieces into Functional Blocks and Distribute Across the Boot Flow
- Summary
- Chapter 11: Intel’s Fast Boot Technology
- Chapter 12: Collaborative Roles in Quick Boot
- Chapter 13: Legal Decisions
-
Appendix A: Generating Serial Presence Detection Data for Down Memory Configurations
- Analyzing the Design’s Memory Architecture
-
Calculating Specific SPD Data Based on SDRAM Datasheet
- SPD Field 0x00: Number of Bytes
- SPD Field 0×01: SPD Revision
- Byte 1: SPD Revision
- SPD Field 0×02: Device Type
- SPD Field 0×03: Module Type
- SPD Field 0×04: SDRAM Density and Banks
- SPD Field 0×05: SDRAM Rows and Columns
- SPD Field 0×06: Nominal Voltage, VDD
- SPD Field 0×07: Ranks & Device DQ Count
- SPD Field 0×08: Module Bus Width
- SPD Field 0×09: Fine Timebase Dividend/Divisor
- SPD Field 0×0A and 0×0B: Medium Timebase Dividend/Divisor
- SPD Field 0x0C: Cycle Time (tCKmin)
- SPD Field 0×0E and 0×0F: CAS Latencies Supported
- SPD Field 0×10: CAS Latency Time (tAAmin or tCL)
- SPD Field 0×11: Write Recovery Time (twrmin)
- SPD Field 0×12 RAS# to CAS# Delay (tRCDmin)
- SPD Field 0x13: Min. Row Active to Row Active Delay (tRRDmin)
- SPD Field 0×14: Min. Row Precharge Delay (tRPmin)
- SPD Field 0×15: Upper Nibble of tRAS & tRC
- SPD Field 0×16: Min. Active to Precharge Delay (tRASmin) LSB
- SPD Field 0×17: Min. Active to Active Refresh Delay (tRCmin) LSB
- SPD Field 0×18 and 0×19: Min. Refresh Recovery Delay (tRFCmin)
- SPD Field 0×1A: Min. Write to Read Command Delay (tWTRmin)
- SPD Field 0×1B: Min. Read to Precharge Command Delay (tRTPmin)
- SPD Field 0×1C: tFAW Upper Nibble
- SPD Field 0×1D: Min. Four Activate Window Delay (tFAWmin) LSB
- SPD Field 0x1E: SDRAM Optional Features
- SPD Field 0×1F: SDRAM Thermal and Refresh Options
- SPD Field 0×20: Module Thermal Sensor
- SPD Field 0x21: SDRAM Device Type
- SPD Field 0×22–0×3B: Reserved
-
Module-Specific Section: Bytes 60–116
- SPD Field 0×3C: (Unbuffered): Module Nominal Height
- SPD Field 0×3D: (Unbuffered): Module Max. Thickness
- SPD Field 0x3E: (Unbuffered): Reference Raw Card Used
- SPD Field 0×3F: Unbuff Addr. Mapping from Edge Connector to DRAM
- SPD Field 0×40-0×74: Reserved
- SPD Field 0×75 and 0×76: Module Manufacturer ID Code, LSB
- SPD Field 0×77: Module Manufacturer Location
- SPD Field 0×78 and 0×79: Module Manufacturing Date
- SPD Field 0x7A–0x7D: Module Serial Number
- SPD Field 0×7E and 0×7F: CRC Bytes
- Bytes 126–127: SPD Cyclical Redundancy Code (CRC)
- SPD Field 0×80–0×91
- SPD Field 0×92 and 0×93: Module Revision Code
- SPD Field 0×94 and 0×95: DRAM Manufacturer ID Code
- SPD Field 0×96–0×AF: Manufacturer’s Specific Data
- SPD Field 0×B0–0×FF: Open for Customer Use
- References for Appendix A
- Index
Product information
- Title: Quick Boot
- Author(s):
- Release date: December 2017
- Publisher(s): De Gruyter
- ISBN: 9781501506727
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