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Quick Boot

Book Description

Quick Boot is designed to give developers a background in the basic architecture and details of a typical boot sequence. More specifically, this book describes the basic initialization sequence that allows developers the freedom to boot an OS without a fully featured system BIOS. Various specifications provide the basics of both the code bases and the standards. This book also provides insights into optimization techniques for more advanced developers. With proper background information, the required specifications on hand, and diligence, many developers can create quality boot solutions using this text.

Pete Dice is Engineering Director of Verifone, where he manages OS Engineering teams in Dublin, Ireland and Riga Latvia. Dice successfully launched Intel® Quark™, Intel's first generation SoC as well as invented the Intel® Galileo™ development board and developed a freemium SW strategy to scale Intel IoT gateway features across product lines. He is also credited with architecting the "Moon Island" software stack and business model.

Table of Contents

  1. Cover
  2. Title Page
  3. Copyright
  4. Contents
  5. Chapter 1: System Firmware’s Missing Link
    1. Start by Gathering Data
      1. Initialization Roles and Responsibilities
      2. System Firmware
      3. OS Loader
      4. Operating System
    2. Legacy BIOS Interface, UEFI, and the Conversion
      1. Tiano Benefits
      2. Previous UEFI Challenges
      3. Persistence of Change
      4. The Next Generation
    3. Commercial BIOS Business
      1. Award
      2. General Software
      3. Phoenix Technologies Limited
      4. American Megatrends Inc.
      5. Insyde Software
      6. ByoSoft
      7. Value of BIOS
    4. Proprietary Solutions
    5. Making a Decision on Boot Firmware
      1. Consider Using a BIOS Vendor
      2. Consider Open-Source Alternatives
      3. Consider Creating Something from Scratch
      4. Consider a Native Boot Loader for Intel ® Architecture
      5. Just Add Silicon Initialization
    6. Summary
  6. Chapter 2: Intel Architecture Basics
    1. The Big Blocks of Intel Architecture
      1. The CPU
      2. The Front Side Bus
      3. The North Bridge, PCIset, AGPset, MCH, Uncore, System Agent
      4. The Transparent Link (Hublink, DMI, ESI)
      5. The South Bridge, Also Known as the PIIX, I/O Controller Hub (ICH), I/O Hub (IOH), Enterprise South Bridge (ESB), and Platform Controller Hub (PCH)
    2. Data Movement Is Fundamental
    3. It’s a Multiprocessing System Architecture
    4. The Memory Map
      1. I/O Address Range
    5. The Operating System
    6. Summary
  7. Chapter 3: System Firmware Terms and Concepts
    1. Typical PC/Intel® Architecture Overview
    2. Memory Types
      1. Processor Cache
      2. System Memory
      3. Complementary Metal-Oxide Semiconductor (CMOS)
      4. System BIOS Flash Memory (NVRAM, FWH, or SPI)
    3. Real-Time Clock (RTC)
    4. System Memory Map
      1. Legacy Address Range
      2. Main Memory Address Range
      3. PCI Memory Address Range
    5. Splash Screen
    6. Status and Error Messages
      1. Display Messages
      2. Beep Codes
      3. POST Codes
    7. Master Boot Record
    8. GUID Partition Table
    9. Real Mode
    10. Protected Mode
      1. Logical Addressing
      2. Flat Protected Mode
    11. Reset Vector
    12. Programmable Interrupt Controller
    13. Advanced Programmable Interrupt Controller
      1. The I/OxAPIC
      2. The Local APIC
    14. Summary
  8. Chapter 4: Silicon-Specific Initialization
    1. Listen to the Designer, Then Experiment, and Fix It
    2. Chipsets
    3. Processors
    4. Basic Types of Initialization
      1. Simple Bits
      2. Standard Algorithms, Minding the Ps and Qs
      3. Custom Algorithms: It’s All About Me
      4. Option ROMs
    5. Summary
  9. Chapter 5: Industry Standard Initialization
    1. PCI
      1. PCI Device Enumeration
      2. PCI BIOS
    2. PCI IRQ Routing with ACPI Methods
    3. PCI Recommendation
      1. PCI Power Management
    4. USB Enumeration and Initialization
      1. PCI Enumeration and Initialization of USB Controllers
      2. USB Wake from ACPI Sx (S3, S4, S5 to S0)
      3. USB Enumeration
    5. SATA
    6. SATA Controller Initialization
      1. Setting the SATA Controller Mode
      2. Enabling SATA Ports
      3. Setting the Programming Interface
      4. Initializing Registers in AHCI Memory-Mapped Space
      5. RAID Mode Initialization
      6. Additional Programming Requirements During SATA Initialization
      7. External SATA Programming
      8. Compliance with Industry Specifications
    7. Advanced Configuration and Power Interface (ACPI)
      1. ACPI Tables
      2. ACPI Namespace
    8. Summary
  10. Chapter 6: System Firmware Debug Techniques
    1. Host/Target Debugging Techniques
    2. Hardware Capabilities
      1. POST Codes
      2. Audio (Beep) Codes
      3. Serial Port
      4. In-Target Probe (ITP), a Form of JTAG Port
    3. Software Debug Methods
      1. Console Input/Output
      2. Abstraction
      3. Disable Optimization
    4. Where Am I in the Firmware?
    5. When Hardware Isn’t Stable, Where Do I Start?
    6. Debugging Other People’s Code
      1. Debugging PCI Option ROMs or Binary Libraries
      2. Debugging Library Code (No Source)
    7. Debugging Beyond Firmware
      1. Real Mode Interrupts
      2. System Management Mode
      3. Industry Specifications
      4. Pitfalls
    8. Summary
  11. Chapter 7: Shells and Native Applications
    1. Pre-OS Shells
    2. UEFI Shell Application
    3. EFI/UEFI Script File
      1. Different Features between Script and App
    4. Customizing the UEFI Shell
    5. Where to Get Shells
    6. GUIs and the UEFI Shell
    7. Remote Control of the UEFI Shell
    8. Debugging Drivers and Applications in the EFI and UEFI Shells
    9. The End for the Shell
    10. Summary
  12. Chapter 8: Loading an Operating System
    1. The Boot Path
      1. The Bus
      2. The Device
      3. The Partition Table
      4. The File System
    2. Booting via the Legacy OS Interface
      1. Master Boot Record
      2. Loading the Legacy OS Loader
      3. Legacy BIOS to OS Handoff Requirements
    3. Booting via the EFI Interface
      1. Default EFI Boot Behavior
      2. Direct Execution of a Linux Kernel
      3. UEFI Runtime Services
    4. Neither Option
    5. Summary
  13. Chapter 9: The Intel ® Architecture Boot Flow
    1. Hardware Power Sequences (The Pre-Pre-Boot)
      1. Nonhost-Based Subsystem Startup
      2. Starting at the Host Reset Vector
      3. Mode Selection
    2. Early Initialization
      1. Single-Threaded Operation
      2. Simple Device Initialization
      3. Memory Configuration
      4. Post-Memory
      5. Shadowing
      6. Exit from No-Eviction Mode and Transfer to DRAM
      7. Transfer to DRAM
      8. Memory Transaction Redirection
      9. Application Processor (AP) Initialization
    3. Advanced Initialization
      1. General Purpose I/O (GPIO) Configuration
      2. Interrupt Controllers
      3. Interrupt Vector Table (IVT)
      4. Interrupt Descriptor Table (IDT)
      5. Timers
      6. Memory Caching Control
      7. Serial Ports
      8. Clock and Overclock Programming
      9. PCI Device Enumeration
      10. Graphics Initialization
      11. Input Devices
      12. USB Initialization
      13. SATA Initialization
      14. SATA Controller Initialization
    4. Memory Map
      1. Region Types
      2. Region Locations
    5. Loading the OS
    6. Summary
  14. Chapter 10: Bootstrapping Embedded
    1. Optimization Using BIOS and Bootloaders
      1. Platform Policy (What Is It and Why Is It Here?)
    2. Case Study Summaries
      1. Example 1
      2. Example 2
    3. Example 1 Details
      1. What Are the Design Goals?
      2. What Are the Supported Target Operating Systems?
      3. Do We Have to Support Legacy Operating Systems?
      4. Do We Have to Support Legacy Option ROMs?
      5. Are We Required to Display an OEM Splash Screen?
      6. What Type of Boot Media Is Supported?
      7. What Is the BIOS Recovery/Update Strategy?
      8. When Processing Things Early
      9. Is There a Need for Pre-OS User Interaction?
      10. A Note of Caution
      11. Additional Details
    4. Example 2 Details
      1. Turn Off Debugging
      2. Decrease Flash Size
      3. Caching of PEI Phase
      4. Intel SpeedStep® Technology Enabled Early
      5. BDS Phase Optimization
      6. Platform Memory Speed
      7. Remove PS/2 Keyboard/Mouse
      8. Remove BIOS Setup
      9. Remove Video Option ROM
      10. Remove BIOS USB Support
      11. Divide Long Lead Pieces into Functional Blocks and Distribute Across the Boot Flow
    5. Summary
  15. Chapter 11: Intel’s Fast Boot Technology
    1. The Human Factor
    2. Responsiveness
    3. The (Green) Machine Factor
    4. Boot Time Analysis
      1. First Boot versus Next Boot Concept
      2. Boot Mode UEFI Configuration Setting
      3. Fallback Mechanisms
    5. Baseline Assumptions for Enabling Intel Fast Boot
    6. Intel Fast Boot Timing Results
    7. Summary
  16. Chapter 12: Collaborative Roles in Quick Boot
    1. Power Hardware Role
      1. Power Sequencing
      2. Power Supply Specification
    2. Flash Subsystem
      1. High Speed SPI Bus for Flash
      2. Flash Component Accesses
      3. SPI Prefetch and Buffer
      4. SPI Flash Reads and Writes
      5. Slow Interface and Device Access
      6. DMI Optimizations
    3. Processor Optimizations
      1. CPU Turbo Enabling
      2. Streamline CPU Reset and Initial CPU Microcode Update
      3. Efficient APs Initialization
      4. Caching Code and Data
    4. Main Memory Subsystem
      1. Memory Configuration Complexity
      2. Fast and Safe Memory Initialization
      3. Hardware-Based Memory Clearing
      4. Efficient Memory Operations Instruction Usage
      5. SMBus Optimizations (Which Applies to Memory Init)
      6. Minimize BIOS Shadowing Size, Dual DXE Paths for Fast Path versus Full Boot
      7. PCIe Port Disable Algorithm
    5. Manageability Engine
      1. Eliminating MEBx
      2. Reducing Manageability Engine and BIOS Interactions
    6. Graphics Subsystem
      1. Graphics Device Selection
      2. Graphics Output Protocol (GOP) Support for CSM-Free Operating Systems
      3. Panel Specification
      4. Start Panel Power Early
    7. Storage Subsystems
      1. Spinning Media
      2. Utilizing Nonblocking Storage I/O
      3. Early SATA COMRESETs: Drive Spin-Up
      4. CSM-Free Intel® Raid Storage Technology (Intel RST) UEFI Driver
      5. Minimizing USB Latency
    8. Power Management
      1. Minimizing Active State Power Management Impact
    9. Security
      1. Intel® Trusted Execution Technology (Intel TXT)
      2. TPM Present Detect and Early Start
    10. Operating System Interactions
      1. Compatibility Segment Module and Legacy Option ROMs
      2. OS Loader
      3. Legacy OS Interface
      4. Reducing Replication of Enumeration Between Firmware and OS
    11. Other Factors Affecting Boot Speed
      1. No Duplication in Hardware Enumeration within UEFI
      2. Minimize Occurrences of Hardware Resets
      3. Intel Architecture Coding Efficiency
      4. Network Boot Feature
      5. Value-Add, But Complex Features
      6. Tools and the User Effect
      7. Human Developer’s Resistance to Change
    12. Summary
  17. Chapter 13: Legal Decisions
    1. Proprietary License
    2. Berkeley Software Distribution (BSD) License
      1. Key Four Clauses to the Original License
      2. Three-Clause BSD
    3. General Public License (GPL)
    4. Lesser GPL (LGPL)
    5. Separating and Segregating Code
    6. Conclusion
  18. Appendix A: Generating Serial Presence Detection Data for Down Memory Configurations
    1. Analyzing the Design’s Memory Architecture
      1. Calculating DIMM Equivalents
      2. ECC Calculation
      3. SDRAM Width Determination
      4. SDRAM Chip Datasheet
      5. SDRAM Architecture Analysis Example
    2. Calculating Specific SPD Data Based on SDRAM Datasheet
      1. SPD Field 0x00: Number of Bytes
      2. SPD Field 0×01: SPD Revision
      3. Byte 1: SPD Revision
      4. SPD Field 0×02: Device Type
      5. SPD Field 0×03: Module Type
      6. SPD Field 0×04: SDRAM Density and Banks
      7. SPD Field 0×05: SDRAM Rows and Columns
      8. SPD Field 0×06: Nominal Voltage, VDD
      9. SPD Field 0×07: Ranks & Device DQ Count
      10. SPD Field 0×08: Module Bus Width
      11. SPD Field 0×09: Fine Timebase Dividend/Divisor
      12. SPD Field 0×0A and 0×0B: Medium Timebase Dividend/Divisor
      13. SPD Field 0x0C: Cycle Time (tCKmin)
      14. SPD Field 0×0E and 0×0F: CAS Latencies Supported
      15. SPD Field 0×10: CAS Latency Time (tAAmin or tCL)
      16. SPD Field 0×11: Write Recovery Time (twrmin)
      17. SPD Field 0×12 RAS# to CAS# Delay (tRCDmin)
      18. SPD Field 0x13: Min. Row Active to Row Active Delay (tRRDmin)
      19. SPD Field 0×14: Min. Row Precharge Delay (tRPmin)
      20. SPD Field 0×15: Upper Nibble of tRAS & tRC
      21. SPD Field 0×16: Min. Active to Precharge Delay (tRASmin) LSB
      22. SPD Field 0×17: Min. Active to Active Refresh Delay (tRCmin) LSB
      23. SPD Field 0×18 and 0×19: Min. Refresh Recovery Delay (tRFCmin)
      24. SPD Field 0×1A: Min. Write to Read Command Delay (tWTRmin)
      25. SPD Field 0×1B: Min. Read to Precharge Command Delay (tRTPmin)
      26. SPD Field 0×1C: tFAW Upper Nibble
      27. SPD Field 0×1D: Min. Four Activate Window Delay (tFAWmin) LSB
      28. SPD Field 0x1E: SDRAM Optional Features
      29. SPD Field 0×1F: SDRAM Thermal and Refresh Options
      30. SPD Field 0×20: Module Thermal Sensor
      31. SPD Field 0x21: SDRAM Device Type
      32. SPD Field 0×22–0×3B: Reserved
    3. Module-Specific Section: Bytes 60–116
      1. SPD Field 0×3C: (Unbuffered): Module Nominal Height
      2. SPD Field 0×3D: (Unbuffered): Module Max. Thickness
      3. SPD Field 0x3E: (Unbuffered): Reference Raw Card Used
      4. SPD Field 0×3F: Unbuff Addr. Mapping from Edge Connector to DRAM
      5. SPD Field 0×40-0×74: Reserved
      6. SPD Field 0×75 and 0×76: Module Manufacturer ID Code, LSB
      7. SPD Field 0×77: Module Manufacturer Location
      8. SPD Field 0×78 and 0×79: Module Manufacturing Date
      9. SPD Field 0x7A–0x7D: Module Serial Number
      10. SPD Field 0×7E and 0×7F: CRC Bytes
      11. Bytes 126–127: SPD Cyclical Redundancy Code (CRC)
      12. SPD Field 0×80–0×91
      13. SPD Field 0×92 and 0×93: Module Revision Code
      14. SPD Field 0×94 and 0×95: DRAM Manufacturer ID Code
      15. SPD Field 0×96–0×AF: Manufacturer’s Specific Data
      16. SPD Field 0×B0–0×FF: Open for Customer Use
    4. References for Appendix A
  19. Index