As FPGA designs increase in size and complexity, the board-level testing effort also increases in complexity. As previously discussed, the design verification phases of a typical FPGA design project including simulation, debug and verification can comprise 40% or more of the overall design cycle. By increasing the efficiency of the verification design phases, the design cycle can be dramatically reduced.
A well-planned design will require some minimum number of hours to verify. The closer a design verification phase can be held to this standard, the shorter the schedule. However, for a poorly conceived or implemented design there is essentially no upper limit in terms of time and resources that may ...