Having introduced the Type 2 and Type 13 transaction packet formats, we can now understand how a Read operation is accomplished in the RapidIO architecture. The Read operation (Figure 4.3) is quite straightforward and serves as a good demonstration of how the RapidIO protocol works. A Read operation is composed of an NREAD transaction and a RESPONSE transaction.

Let's assume that a processor intends to read the contents of a memory-mapped register on a peripheral device across a RapidIO interconnect. To do this, the processor will produce an NREAD transaction and send it to the peripheral. The peripheral will retrieve the contents of the register and use it as the payload of a RESPONSE transaction that will be sent back to the processor. We will make the following assumptions for this example.

  1. The processor or source has a RapidIO deviceID of 0×10

  2. The peripheral or target has a RapidIO deviceID of 0×36

  3. The memory address to be read on the peripheral is 0×ffff0004 and is 4 bytes in length. The address space on the peripheral is addressable with 32 bits.

The RapidIO interface logic on the processor prepares the packet for the transaction that will be sent to the peripheral. Figure 4.4 shows all 12 bytes of this transaction. Working from left to right and from top to bottom, the fields in this transaction are as follows. The physical layer fields make up the first ten bits of this packet. They will be described in detail in a later section. The next 2 bits ...

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