RapidIO: The Next Generation Communication Fabric For Embedded Application

8.14. BOARD ROUTING GUIDELINES

This section contains board design guidelines for RapidIO-based systems. The information here is presented as a guide for implementing a RapidIO board design. It is noted that the board designer may have constraints such as standard design practices, vendor selection criteria, and design methodology that must be followed. Therefore appropriate diligence must be applied by the designer.

Parallel RapidIO is a source-synchronous differential point-to-point interconnect, so routing considerations are minimal. The very high clock rate places a premium on minimizing skew and discontinuities, such as vias and bends. Generally, layouts should be as straight and free of vias as possible, with controlled impedance differential pairs.

8.14.1. Impedance

Interconnect design should follow standard practice for differential pairs. To minimize reflections from the receiver's 100 Ω termination, the differential pair should have an differential impedance of 50 Ω. The two signals forming the differential pair should be tightly coupled. The differential pairs should be widely spaced, although consistent with skew control and quality routing constraints, so that the crosstalk noise is limited.

8.14.2. Skew

To minimize the skew on a RapidIO channel the total electrical length for each trace within each unidirectional channel should be equal. Several layouts are suggested in Figure 8.22. Because the parallel RapidIO interface is source synchronous, the total length is ...