9.6. INTERACTIONS WITH GLOBALLY SHARED MEMORY
Traditional systems have two notions of system or subsystem cache coherence. The first, non-coherent, means that memory accesses have no effect on the caches in the system. The memory controller reads and writes memory directly, and any cached data becomes incoherent in the system. This behavior requires that all cache coherence with I/O be managed by software mechanisms, as illustrated in Figure 9.8. In this example the processors and potentially cached contents of local memory are unaware of the request and response transactions to local memory. Software mechanisms must be used to signal changes to local memory so that the caches can be appropriately updated.
The second notion of system cache coherence is that of global coherence. In this scenario, an I/O access to memory will cause a snoop cycle to be issued on the processor bus, keeping all of the system caches coherent with the memory as illustrated in Figure 9.9. Owing to the snoop transaction running on the local interconnect the cache memories are given visibility to the change in the memory contents and may either update their caches with the proper contents or invalidate their copy of the data. Either approach results in correct coherent memory operations.
The example in Figure 9.9 works for systems with traditional bus structures. In RapidIO-based systems there is no common bus that can be used to issue the snoop transaction to. In this type of system global coherence requires ...
