RapidIO: The Next Generation Communication Fabric For Embedded Application

14.1. INTRODUCTION

The RapidIO interconnect technology enables a broad range of system applications by providing a feature rich and layered architecture. As has already been discussed in this book, the RapidIO architecture is segmented into logical, transport and physical layers.

The logical layer supports a variety of programming models, enabling devices to choose a transaction model suitable for the specific application. Examples include DMA transactions, direct processor-to-processor messages and streaming data flows.

The transport layer supports both small and large networks, allowing devices a flexible network topology. Hundreds to thousands of devices are easily supported in a single RapidIO network.

The defined physical layers support latency-tolerant backplane applications as well as latency-sensitive memory applications. RapidIO's layered architecture allows different device implementations to co-exist under a unified hardware/software base. This reduces or eliminates the need for bridging technology and additional protocol conversion overhead.

Device implementations of RapidIO can be broadly classified as end points and switches. End points source and sink transactions to and from the RapidIO network. Switches route packets across the RapidIO network (Figure 14.1 from source to destination, using the information in the packet header, without modifying the logical layer or transport layer of the packet. Switches determine the network topology and play an important role ...