RapidIO: The Next Generation Communication Fabric For Embedded Application

D.2. NEW ERROR MANAGEMENT REGISTER

This section describes the extended features block (EF_ID=0h0007) that allows an external processing element to manage the error status and reporting for a processing element. This appendix describes only registers or register bits defined by this extended features block. All registers are 32 bits and aligned to a 32-bit boundary.

Table D.1. Bit settings for port n control CSRs

Bit	Name	Reset value	Description
28	Stop on port failed-encountered enable	0b0	This bit is used with the drop-packet enable bit to force certain behavior when the error rate failed Threshold has been met or exceeded.
29	Drop-packet enable	0b0	This bit is used with the stop on port failed-encountered enable bit to force certail behavior when the error rate failed threshold has been met or exceeded.
30	Port lockout	0b0	When this bit is cleared, the packets that may be received and issued are controlled by the state of the output port enable and input port enable bits in the port n control CSR When this bit is set, this port is stopped and is not enabled to issue or receive any packets; the input port can still follow the training procedure and can still send and respond to link-requests; all received packets return packet-not-accepted control symbols to force an error condition to be signaled by the sending device

Table D.2. Bit settings for port n error and status CSRs

Bit	Name	Reset value	Description
5	Output packet-dropped	0b0	Output port has discarded a packet. Once set remains set until written ...