RapidIO: The Next Generation Communication Fabric For Embedded Application

7.3. PCS AND PMA LAYERS

This section describes the functions provided by the Physical coding sublayer (PCS) and Physical media attachment (PMA) sublayer. (The PCS and PMA terminology is adopted from IEEE 802.3). The topics include 8B/10B encoding, character representation, serialization of the data stream, code groups, columns, link transmission rules, idle sequences, and link initialization.

The concept of lanes is used to describe the width of a Serial RapidIO link. A lane is defined as one unidirectional differential pair in each direction. Serial RapidIO currently specifies two link widths. The 1x link is a one-lane link and the 4x link is a 4-lane link. Wider links are possible, but are not currently specified.

Figure 7.16 shows the structure of a typical Serial RapidIO end point. At the top of the diagram are the logical and transport layers that are responsible for the creation of the bulk of the RapidIO packet itself. Immediately below these layers is the serial protocol layer which is responsible for generation and consumption of control symbols and for managing the link through the link management protocol. Below this layer is the PCS layer. The boundary between the link protocol management layer and the PCS layer will typically be where the clock boundary changes from that used internal to the device to that used for the RapidIO end point itself. The PCS layer is responsible for lane striping, idle sequence generation and character conversion to the appropriate 8B/10B ...