RapidIO: The Next Generation Communication Fabric For Embedded Application

C.3. SWITCH DEVICES

This section describes the 8/16 LP-LVDS registers for generic devices that do not contain end point functionality. Typically these devices are switches. This extended features register block uses extended features block ID=0×0003.

C.3.1. Register Map

Table C.21 shows the register map for generic RapidIO 8/16 LP-LVDS end point-free devices. The block offset is the offset based on the extended features pointer (EF_PTR) to this block. This register map is currently defined only for devices with up to 16 RapidIO ports, but can be extended or shortened if more or less port definitions are required for a device. For example, a device with four RapidIO ports is only required to use register map space corresponding to offsets [EF_PTR +0×00] through [EF_PTR +0×98]. Register map offset [EF_PTR +0×A0] can be used for another extended features block.

Table C.21. Physical 8/16 LP-LVDS Register Map

Block byte offset	Register name (Word 0)	Register name (Word 1)
0×0	8/16 LP-LVDS port maintenance block header
0×8–18	Reserved
0×20	Port link time-out control CSR	Reserved
0×28	Reserved
0×30	Reserved
0×38	Reserved	Port general control CSR
0×40	Reserved
0×48	Reserved
0×50	Reserved
0×58	Port 0 error and status CSR	Port 0 control CSR
0×60	Reserved
0×68	Reserved
0×70	Reserved
0×78	Port 1 error and status CSR	Port 1 control CSR
0×80–218	Assigned to port 2–14 CSRs
0×220	Reserved
0×228	Reserved
0×230	Reserved
0×238	Port 15 error and status CSR	Port 15 control CSR

C.3.2. Command and Status Registers (CSRs)

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