RapidIO: The Next Generation Communication Fabric For Embedded Application

7.4. USING THE SERIAL PHYSICAL LAYER

Now that we have covered the bits that make up the serial physical layer header, the control symbols that are used to manage the communications between the ports and the encoding of the bit streams using the 8B/10B technique to include both clocking and DC balance into the signal, we can examine how the link actually works to send data between two end points.

7.4.1. Port Initialization Process

Port initialization is the process that RapidIO uses to initialize and synchronize a pair of ports for communications. This process includes detecting the presence of a partner at the other end of the link (a link partner), establishing bit synchronization and code group boundary alignment and if the port is capable of supporting both 1x and 4x modes (a 1x/4x port), discovering whether the link partner is capable of 4x mode (4-lane) operation, selecting 1x or 4x mode operation and if 1x mode is selected, selecting lane 0 or lane 2 for link reception.

Several state machines control the initialization process. The RapidIO specification presents details on the structure of the state machines. The number and type of state machines depends on whether the port supports only 1x mode (a 1x port) or supports both 1x and 4x modes (a 1x/4x port). In either case, there is a primary state machine and one or more secondary state machines. The use of multiple state machines results in a simpler overall design. As might be expected, the initialization process for a ...