68 Real-time systems development
MOV A, T ; normal operation if T=1
MOVX @R0, A
INC R0
SWAP A
MOVX @R0, A
ORL P2, #0FFH ;deselect backup RAM
CLEAR: MOV R7, #0FFH ;
MOV R6, #0DEH ;clear display
CALL DISPR
MOV R6, #07BH ;
CALL DISPR
JF1 PF2
ORL P1, #040H ;kill processor thro reset line
PF2: MOV R5, #00FH ;if INTEMPT low reset X counter
CALL SWTEST
MOV A, #00H
CALL DELAY
JMP RESET ;jump to reset if KILL fails
3.11 Interrupt structure on the PC
Extra hardware can be employed to prioritize the incoming interrupt signals,
as with the Intel PIC (Programmable Interrupt Controller) chip which allows
through a single IRQ from the most urgent device. Even then, the CPU may
still not accept the request because it has disabled all interrupt processing.
The Pentium has a CPU status flag which indicates whether it is prepared to
respond to interrupts or not. To control this, there is a pair of instructions to
set and clear the interrupt flag: STI and CLI. However, these instructions
are only available to privileged users.
Once an interrupt is accepted by the CPU there remains the problem
of identifying the source of the request and then locating the correct ISR
in memory. The PIC identifies which IRQ was responsible for the interrupt.
However, when asked by the CPU for the identification it does not return the
IRQ number, but an 8 bit number, known as the vector. This is used by the
CPU to access the correct entry in the IVT (Interrupt Vector Table) held in
memory. The IVT data table holds the addresses of the entry points for all
possible ISRs. Every source of interrupt has a unique entry in this address
table or IVT (Interrupt Vector Table).
The relatively small number of interrupt lines available on the PC would
seem to be a major disadvantage when trying to add further devices. But so
far people have got by, often by disabling existing devices or even unplugging
boards in order to share an IRQ. Suffering an IRQ conflict was a common
problem when installing new ISA cards. PCI cards share the primary IRQ
levels allocated to the bus.
Basic input and output 69
PIC 2
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
PIC 1
IRQ0
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
to
Pentium
interrupt
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
PIC Interrupt Mask Register (21H)
1 – disable
0 – enable
PIC Interrupt Control Register (20H)
EOI – write 1, re-enable interrupts
I
0
– I
2
– read, current interrupt number
I
0
I
1
I
2
00EOI
Int Function Source
Number
77 Hard Disk2 IRQ15
IRQ1476 Hard Disk1
75 8087 IRQ13
IRQ1274 PS/2 mouse
73 Soundcard
Network
IRQ11
72 IRQ10
IRQ2
IRQ8
71 Redirected
70 RTC
18
BIOS/TOD
BIOS/softboot
BIOS/print
BIOS/KBD
BIOS/comms
BIOS/disk
BIOS/msize
17 INT
INT
16 INT
15 INT
14 INT
13 INT
12 INT
INT
INT
11 BIOS/check
10 BIOS/video
LPT1:
KBD:
COM1:
COM2:
----
FDC
SoundCard
0F IRQ7
0E IRQ6
0D IRQ5
0C IRQ4
0B IRQ3
0A IRQ2
09 IRQ1
IRQ008 System timer
07
06
05 Screen dump to printer
04 Numeric overflow
03 Breakpoint
02 NMI, power fail
01 Single step trace
00 Integer divide error
Part of the PC interrupt vector table and related PIC connections
The highest priority is IRQ0, with IRQ15 the lowest and not all the IRQ lines
are mapped through to the ISA and PCI expansion buses.
IRQ0 committed for the principal system timer. This generates the ticks
which enable the operating system (Unix, Windows) to regain control
from any process at the end of its allocated time slot.
IRQ1 – committed to the keyboard controller.
IRQ2 committed to the cascaded, second PIC which offers IRQ8–IRQ15.
IRQ9 takes on the role of IRQ2 inputs, but is not commonly used, to
avoid the possibility of conflict.
IRQ3 designated as COM2 serial port, but widely used for modems
internal as well as external, which leads to frequent conflicts. This may
be avoided by relocating the modem to an unused IRQ, or disabling the
COM2 activity in the BIOS setup parameters. Sometimes a sound card

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