68 Real-time systems development
MOV A, T ; normal operation if T=1
MOVX @R0, A
MOVX @R0, A
ORL P2, #0FFH ;deselect backup RAM
CLEAR: MOV R7, #0FFH ;
MOV R6, #0DEH ;clear display
MOV R6, #07BH ;
ORL P1, #040H ;kill processor thro reset line
PF2: MOV R5, #00FH ;if INTEMPT low reset X counter
MOV A, #00H
JMP RESET ;jump to reset if KILL fails
3.11 Interrupt structure on the PC
Extra hardware can be employed to prioritize the incoming interrupt signals,
as with the Intel PIC (Programmable Interrupt Controller) chip which allows
through a single IRQ from the most urgent device. Even then, the CPU may
still not accept the request because it has disabled all interrupt processing.
The Pentium has a CPU status ﬂag which indicates whether it is prepared to
respond to interrupts or not. To control this, there is a pair of instructions to
set and clear the interrupt ﬂag: STI and CLI. However, these instructions
are only available to privileged users.
Once an interrupt is accepted by the CPU there remains the problem
of identifying the source of the request and then locating the correct ISR
in memory. The PIC identiﬁes which IRQ was responsible for the interrupt.
However, when asked by the CPU for the identiﬁcation it does not return the
IRQ number, but an 8 bit number, known as the vector. This is used by the
CPU to access the correct entry in the IVT (Interrupt Vector Table) held in
memory. The IVT data table holds the addresses of the entry points for all
possible ISRs. Every source of interrupt has a unique entry in this address
table or IVT (Interrupt Vector Table).
The relatively small number of interrupt lines available on the PC would
seem to be a major disadvantage when trying to add further devices. But so
far people have got by, often by disabling existing devices or even unplugging
boards in order to share an IRQ. Suﬀering an IRQ conﬂict was a common
problem when installing new ISA cards. PCI cards share the primary IRQ
levels allocated to the bus.
Basic input and output 69
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
PIC Interrupt Mask Register (21H)
1 – disable
0 – enable
PIC Interrupt Control Register (20H)
EOI – write 1, re-enable interrupts
– read, current interrupt number
Int Function Source
77 Hard Disk2 IRQ15
IRQ1476 Hard Disk1
75 8087 IRQ13
IRQ1274 PS/2 mouse
IRQ008 System timer
05 Screen dump to printer
04 Numeric overflow
02 NMI, power fail
01 Single step trace
00 Integer divide error
Part of the PC interrupt vector table and related PIC connections
The highest priority is IRQ0, with IRQ15 the lowest and not all the IRQ lines
are mapped through to the ISA and PCI expansion buses.
IRQ0 – committed for the principal system timer. This generates the ticks
which enable the operating system (Unix, Windows) to regain control
from any process at the end of its allocated time slot.
IRQ1 – committed to the keyboard controller.
IRQ2 – committed to the cascaded, second PIC which oﬀers IRQ8–IRQ15.
IRQ9 takes on the role of IRQ2 inputs, but is not commonly used, to
avoid the possibility of conﬂict.
IRQ3 – designated as COM2 serial port, but widely used for modems
internal as well as external, which leads to frequent conﬂicts. This may
be avoided by relocating the modem to an unused IRQ, or disabling the
COM2 activity in the BIOS setup parameters. Sometimes a sound card