Chapter 8. Programming Streaming FPGA Applications Using Block Diagrams in Simulink
Brian C. Richards, Chen Chang, John Wawrzynek, Robert W. BrodersenDepartment of Electrical Engineering and Computer Science University of California–Berkeley
Although a system designer can use hardware description languages, such as VHDL (Chapter 6) and Verilog to program field-programmable gate arrays (FPGAs), the algorithm developer typically uses higher-level descriptions to refine an algorithm. As a result, an algorithm described in a language such as Matlab or C is frequently reentered by hand by the system designer, after which the two descriptions must be verified and refined manually. This can be time consuming.
To avoid reentering a design when translating ...
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