Chapter 12. The JHDL Design and Debug System
Brent Nelson, Brad HutchingsDepartment of Electrical and Computer EngineeringBrigham Young University
JHDL [1, 8] is a CAD environment developed at Brigham Young University for the design, debug, and runtime control of configurable computing applications based on field-programmable gate array (FPGA) technology. Developed roughly between 1997 and 2003 it was made available under an open-source license (http://www.jhdl.or g) in approximately 2000. The term JHDL can refer to one of two things: (1) the JHDL circuit design language itself, or (2) the JHDL CAD system. The JHDL language is a text-based design language for algorithmic construction of structured circuits that is embedded within the Java programming ...
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