In addition to the bandwidth rating of a memory module, such as PC3200 or PC2-6400, several other numbers are used to quantify memory performance. These values, known as timing parameters, quantify the response time and latency of the module. Memory is Figure 6-3. Types of memory used in new structured like a spreadsheet, with many columns and many rows, each of systems by year which contains one bit of data. Timing parameters specify the time required to perform such functions as changing the row or column and reading data. (It's not important to understand timing parameters except in a general, overall sense.)
For DDR-SDRAM and DDR2-SDRAM, memory vendors specify values, denominated in whole or fractional clock cycles, for the following four timing parameters:
CAS Latency (Column Access Strobe Latency), or tCL, specifies the number of clock cycles between the column strobe signal and when data is available on the output pins. During sequential memory accesses, the row remains activated and only the column changes, which means that the time required to change columns is critical to overall memory performance. CAS Latency, often abbreviated CL, is the most commonly quoted timing parameter and the most important memory timing parameter with respect to overall performance.
RAS to CAS Delay (Row Access Strobe to CAS Delay), or tRCD, specifies the number of clock cycles between the time a row is activated by the row strobe until the column ...