9.1 Objectives

Look at upcoming wafer fabrication developments and how they will affect semiconductor packaging technology.

9.2 Introduction

This chapter looks at the continued scaling of silicon complementary metal oxide semiconductor (CMOS) chips and the issues imposed on assembly and packaging requirements by the new materials set used to create these integrated circuits. There is also some discussion of what may be required of semiconductor packaging once Moore’s Law can no longer be sustained.

9.3 Copper interconnects and low-к dielectric materials

According to the 2007 update to the Interconnect chapter, ITRS (International Technology Roadmap for Semiconductors) noted that as far back as 1994 ...

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