MOS Transistor Operation and Integrated Circuit Fabrication
This chapter gives a review of the operation of the metal oxide semiconductor (MOS) transistor [22–24] together with the technological processes employed in the fabrication of MOS transistors and integrated circuits. Knowledge of device physics is assumed, including the operation of the pn junction and basic transistor operation. The chapter begins with a review of the MOS transistor operation equations and introduces the complementary (CMOS) circuits. A description is next given of the fabrication of MOS devices which is necessary for understanding the performance and limitations of MOS integrated circuits used in signal processing. Layout rules and area requirements of integrated circuits are described. The chapter concludes by a discussion of the subject of noise in MOSFETs.
Figure 10.1 shows the physical structure of an n- channel enhancement-type MOSFET. The device is fabricated on a p-type substrate consisting of a single-crystal silicon wafer. The n+ regions are heavily-doped n-type silicon, constituting the source and drain regions. A thin silicon dioxide (SiO2) layer is grown on the substrate, extending over the area between the source and drain. For the electrodes, metal can be used as contacts to the gate, source, drain and substrate. The gate electrode can also be made from poly-crystalline silicon (polysilicon) in the process of silicon-gate technology. ...