Protecting against electrostatic discharge (ESD) in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) manufactured using silicon-on-insulator (SOI) technology

M.G. Khazhinsky,    Silicon Laboratories, USA


This chapter describes key differences of ESD protection in SOI technologies as compared to bulk. It presents active rail clamp based SOI ESD protection network and design methodology including both device and circuit level characterization data. A compact model is introduced to describe the gated diode in the ESD regime. ESD characteristics of FinFETs, FinDiodes and FDSOI devices as likely device candidates for advanced SOI technologies are studied. A response surface method to conveniently optimize ESD device ...

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