Clocking is a key challenge for high-speed circuit designers. Circuit designers specify a modest number of logical clocks that ideally arrive at all points on the chip at the same time. For example, flip-flop-based systems use a single logical clock, while skew-tolerant domino might use four logical clocks. Unfortunately, mismatched clock network paths and processing and environmental variations make it impossible for all clocks to arrive at exactly the same time, so the designer must settle for actually receiving a multitude of skewed physical clocks. To achieve low clock skew, it is important to carefully match all of the paths ...

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