Prediction is very difficult, especially if it’s about the future.
As cycle times in high-performance digital systems shrink faster than mere process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. Flip-flops and traditional domino circuits, in particular, suffer from clock skew, latch delay, and the inability to balance logic between cycles through time borrowing. The overhead of traditional domino circuits can waste 25% or more of the cycle time in aggressive systems! Fortunately, the designer can hide much of this overhead through better design techniques. Static pipelines ...