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Skew-Tolerant Circuit Design by David Harris

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B

Solutions to Even-Numbered Exercises

1.2. Overhead = ΔCQ + ΔDC + tskew = 330 ps. This is 20% of a 600 MHz cycle and 33% of a 1 GHz cycle.

1.4. Overhead = 2ΔCQ = 2.6 FO4 delays = 156 ps. This is 9% of a 600 MHz cycle and 16% of a 1 GHz cycle. Note that clock skew does not impact the cycle time in a system built from transparent latches.

1.6. Δlogic = TcCQ + ΔDC + tskew) = 5 ns – (0.427 ns + 0.018 ns + 0.4 ns) = 4.155 ns.

1.8. See Table B.1 Tc = 3/N + (0.1 + 0.12 + 0.05). Frequency = 1/Tc. Latency = N · Tc.

Table B.1

Clock frequency and computation latency

# Cycles (N) Max frequency (MHz) Total latency (ns)
1 305 3.27
2 564 3.54
3 787 3.81
4 980 4.08

1.12. Tc = Δlogic + 2ΔDC + 2tskew = 1380 ps. 27% of this time is overhead. ...

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