Solaris™ Internals: Core Kernel Components

5.9. The Hardware Address Translation Layer

The hardware address translation (HAT) layer controls the hardware that manages mapping of virtual to physical memory. The HAT layer provides interfaces that implement the creation and destruction of mappings between virtual and physical memory and provides a set of interfaces to probe and control the MMU. The HAT layer also implements all of the low-level trap handlers to manage page faults and memory exceptions. Figure 5.26 shows the logical demarcation between elements of the HAT layer.

Figure 5.26. Role of the HAT Layer in Virtual-to-Physical Translation

The HAT implementation is different for each ...