Bus Architectures Overview

There are two things to consider about bus performance. The peak data rate is easily quoted, but the ability of the devices on the bus to source or sink data at that rate for more than a few cycles is the real limit to performance. The second consideration is whether the bus protocol includes cycles that do not transfer data, thus reducing the sustained data throughput.

Older buses like VMEbus usually transfer one word at a time, so each bus cycle includes the overhead of deciding which device will access the bus next (arbitration) as well as setting up the address and transferring the data. This procedure is rather inefficient, so more recent buses like SBus, MBus, and UPA transfer data in blocks. Arbitration can ...

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