Memory Management Unit Designs

Unlike many other processor architectures, the memory management unit is not specified as part of the SPARC architecture. This permits great flexibility of implementation, and over the years several very different MMU designs have been implemented. These designs vary depending upon the cost, level of integration, and functionality required for the system design.

The Sun-4 MMU: sun4, sun4c, sun4e Kernel Architectures

Older Sun machines use a “Sun-4™” hardware memory management unit that acts as a large cache for memory translations. It is much larger than the MMU translation cache found on more recent systems, but the entries in the cache, known as PMEGs, are larger and take longer to load. A PMEG is a Page Map ...

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