Synchronous Precharge Logic

3

Transistor Sizing

Proper precharge circuit sizing means adjusting the evaluation stack and output inverter sizes so that the gate is near minimum delay, while still allowing for proper precharge timing. Sizing precharge gates to achieve minimum delay will result in a circuit that is too large in area and power. Instead, the gate should be sized for near minimum delay.

As a rule of thumb, follow this procedure:

1. Estimate the lumped load.

2. Use fanout (FO)=4 to do the sizing of the static gate.

3. Use FO=2–2.75 for the precharge pulldown stack.

4. Run a simulation to check if edge rates are within range.

5. Optimize sizing for minimum delay while keeping edge rates in range.

3.1 Sizing the Pulldown Stack

In order to achieve reasonable sized gates ...