Synchronous Precharge Logic

5

Topology Considerations

5.1 Limitation on Device Stacking

In modern processes, it is inefficient to implement a function with more than four stacked devices in a single evaluation stack. This means one can implement an AND3 with an evaluation footer or an AND4 without the footer.

5.2 Limitation of Logic Width

The problem with wide precharge OR gates is that the keeper quickly becomes large with respect to the pulldowns. This creates writability problems. Additionally, the parasitic capacitance on the internal dynamic net will become significant (also a speed issue). So it is recommended that a wide dynamic OR gate be limited to no more than 8 inputs.

5.3 Use of Low/High V_t Transistors

Modern processes allow for three types of threshold voltages: ...