Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

11

ADDERS AND SUBTRACTORS

Two-operand addition is a primitive operation included in practically all arithmetic algorithms. As a consequence, the efficiency of an arithmetic circuit strongly depends on the way the adders are implemented. A key point in two-operand adder implementation is the way the carries are computed. It has been seen in Chapter 4 that the computation time of a circuit based on the classical pencil and paper algorithm is proportional to the number n of digits of the operands. If this type of algorithm is used, it is important to reduce the multiplicative constant (delay per digit). Another option is to reduce the value of n, that is, to change the numeration system base. In order to get very fast adders, some of the logarithmdelay algorithms presented in Chapter 4 can be used. Another important topic, dealt with in this chapter, is the implementation of multioperand adders. The stored-carry form encoding defined in Chapter 4 is used to synthesize fast multioperand adders. Some ideas for implementing (relatively) low-cost and fast asynchronous adders are presented in the last section.