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Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems by Gustavo D. Sutter, Gery J.A. Bioul, Jean-Pierre Deschamps

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6.4 BIBLIOGRAPHY

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[ATK1968] D. E. Atkins, Higher-radix division using estimates of the divisor and partial remainders. IEEE Trans. Comput., C-17(10): 925–934 (1968).

[BRI1993] W. S. Briggs and D.W. Matula, A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency. In: Proceedings of the 11th IEEE Symposium on Computer Arithmetic, July 1993, pp. 163–170.

[COR1999] M. A. Cornea-Hasegan, R. A. Golliver, and P. Markstein, Correctness proofs outline for Newton–Raphson based floating-point divide and square root algorithms: In: Proceedings of the 14th IEEE Symposium on Computer Arithmetic, 1999, pp. 96–105.

[DAS1995] D. DasSarma and D. W. Matula, Faithfull bipartite ROM reciprocal tables. In Proceedings of the 12th IEEE Symposium Computer Arithmetic, 1995 pp. 17–28.

[EDE1997] A. Edelman, The mathematics of the Pentium division bug. SIAM Rev. 39(1): 54–67 (1997).

[ERC1983] M. D. Ercegovac, A higher radix division with simple selection of quotient digits. In Proceedings of the 6th IEEE Symposium Computer Arithmetic, July 1983, pp. 94–98.

[ERC1987] M. D. Ercegovac and T. Lang, On-the-fly conversion of redundant into conventional representations. IEEE Trans. Comput., 36(7): 895–897 (1987).

[ERC1990] M. D. Ercegovac and T. Lang, Simple radix-4 division with operands scaling. IEEE ...

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