References
[Axel K.Kloth] Axel K. Kloth: Advanced Router Architectures, CRC, 2005, ISBN 0849335507.
[Concurrency-Pillars] Herb Sutter, ‘The Pillars of Concurrency’, Dr. Dobbs magazine, July 02, 2007.
[DPI-XML-IBM] S. Letz, R. Seiffert, J. van Lunteren, and P. Herrmann, ‘System Architecture for XML Offload to a Cell Processor-Based Workstation’, Proceedings of the XML 2005 Conference (XML2005), Atlanta, GA, USA, November 2005.
[FPGA-ASIC] Ian Kuon, Jonathan Rose: Quantifying and Exploring the Gap Between FPGAs and ASICs, Springer, 2009, ISBN 1441907386.
[FPGA-MATLAB] P. Banerjee, et al., ‘Making Area-Performance Tradeoffs at the High Level Using the AccelFPGA Compiler for FPGAs,’ In Proceedings of International Symposium on Field Programmable Gate Arrays, pp. 237, 2003. http://www.portal.acm.org/citation.cfm?id=611817.611854.
[FPGA-MediaBench] Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith, ‘MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems’. http://www.citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.12.2091.
[FPGA-RAW] Babb, J.; Frank, M.; Lee, V.; Waingold, E.; Barua, R.; Taylor, M.; Kim, J.; Devabhaktuni, S.; Agarwal, A. FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium, 16–18 Apr 1997, pp. 134–143.
[GODSON] Weiwu Hu, Jian Wang, Xiang Gao, Yunji Chen, Qi Liu, GODSON-3: A Scalable Multicore RISC Processor with X86 Emulation, IEEE Micro, 29(2), 2009, pp. 17–29.
[GPU-Database] Andrea Di Blas, ...
