Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

Contents

Preface

About the Editors

Contributors

1 Fundamentals of Small-Delay Defect Testing

Sudhakar M. Reddy and Peter Maxwell

Section I Timing-Aware ATPG

2 K Longest Paths

Duncan M. (Hank) Walker

3 Timing-Aware ATPG

Mark Kassab, Benoit Nadeau-Dostie, and Xijiang Lin

Section II Faster-than-at-Speed

4 Faster-than-at-Speed Test for Screening Small-Delay Defects

Nisar Ahmed and Mohammad Tehranipoor

5 Circuit Path Grading Considering Layout, Process Variations, and Cross Talk

Ke Peng, Mahmut Yilmaz, and Mohammad Tehranipoor

Section III Alternative Methods

6 Output Deviations-Based SDD Testing

Mahmut Yilmaz

7 Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects

Sandeep K. Goel and Narendra Devta-Prasanna

8 Circuit Topology-Based ...