April 2011
Intermediate to advanced
552 pages
12h 18m
English
Content preview from The Definitive Guide to the ARM Cortex-M0
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Appendix D. NVIC, SCB, and SysTick Registers Quick Reference
NVIC Register Summary
| Address | Name | CMSIS Symbol | Full Name |
|---|---|---|---|
| 0xE000E100 | ISER | NVIC->ISER | Interrupt Set Enable Register |
| 0xE000E180 | ICER | NVIC->ICER | Interrupt Clear Enable Register |
| 0xE000E200 | ISPR | NVIC->ISPR | Interrupt Set Pending Register |
| 0xE000E280 | ICPR | NVIC->ICPR | Interrupt Clear Pending Register |
| 0xE000E400 | IPR0-7 | NVIC->IPR[0] to NVIC->IPR[7] | Interrupt Priority Register |
Interrupt Set Enable Register (NVIC -> ISER)
To enable an interrupt with a CMSIS-compliant device driver library, please use the
NVIC_EnableIRQ function:
| Address | Name | Type | Reset Value | Descriptions |
|---|---|---|---|---|
| 0xE000E100 | SETENA | R/W | 0x00000000 | Set enable for Interrupts 0 to 31; write 1 to set bit to 1, write 0 has no effect Bit[0] for Interrupt #0 (exception #16) Bit[1] for ... |
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