NVIC and SCB Registers Quick Reference
F.1 NVIC registers
F.1.1 Interrupt set enable registers
Table F.1
Interrupt Set Enable Registers (0xE000E100-0xE000E11C)
F.1.2 Interrupt clear enable registers
Table F.2
Interrupt Clear Enable Registers (0xE000E180-0xE000E19C)
F.1.3 Interrupt set pending registers
Table F.3
Interrupt Set Pending Registers (0xE000E200-0xE000E21C)
F.1.4 Interrupt clear pending registers
Table F.4
Interrupt Clear Pending ...
Get The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors, 3rd Edition now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.