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The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors, 3rd Edition
book

The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors, 3rd Edition

by Joseph Yiu
October 2013
Intermediate to advanced content levelIntermediate to advanced
864 pages
23h 12m
English
Newnes
Content preview from The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors, 3rd Edition
Appendix F

NVIC and SCB Registers Quick Reference

F.1 NVIC registers

F.1.1 Interrupt set enable registers

Table F.1

Interrupt Set Enable Registers (0xE000E100-0xE000E11C)

Image

F.1.2 Interrupt clear enable registers

Table F.2

Interrupt Clear Enable Registers (0xE000E180-0xE000E19C)

Image

F.1.3 Interrupt set pending registers

Table F.3

Interrupt Set Pending Registers (0xE000E200-0xE000E21C)

Image

F.1.4 Interrupt clear pending registers

Table F.4

Interrupt Clear Pending ...

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Publisher Resources

ISBN: 9780124080829