Appendix G

Cortex®-M3/M4 Debug Components Programmer’s Model

G.1 Processor core debug registers

Table G.1

Summary of Processor Core Debug Registers

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Table G.2

Debug Halting Control and Status Register (CoreDebug->DHCSR, 0xE000EDF0)

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These control bits in DHCSR are reset by power on reset and not by system reset.

Table G.3

Debug Core Register Selector Register (CoreDebug->DCRSR, 0xE000EDF4)

Table G.4

Debug Core Register Data Register (CoreDebug->DCRDR, ...

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