October 2013
Intermediate to advanced
864 pages
23h 12m
English
Cortex®-M3/M4 Debug Components Programmer’s Model
Table G.1
Summary of Processor Core Debug Registers

Table G.2
Debug Halting Control and Status Register (CoreDebug->DHCSR, 0xE000EDF0)


∗These control bits in DHCSR are reset by power on reset and not by system reset.
Table G.3
Debug Core Register Selector Register (CoreDebug->DCRSR, 0xE000EDF4)
Table G.4
Debug Core Register Data Register (CoreDebug->DCRDR, ...